1. Field of the Invention
Example embodiments relate to test circuits of a semiconductor memory device for multi-chip testing and methods for testing the multi-chips.
2. Description of Related Art
In general, semiconductor memory devices, e.g., dynamic random access memories (DRAMs), may require a correct data read and write operation, which may be realized when there is no memory cell failure in a semiconductor chip. However, as semiconductor chips become highly integrated, more memory cells may be required, which may result in more failures, even though the memory cells may be fabricated using advanced fabrication techniques. Accordingly, if cells are not correctly tested for failures, semiconductor memory devices may lose their reliability.
However, testing a highly integrated semiconductor memory device on a cell-by-cell basis may increase test time and cost. Accordingly, to reduce the test time of the semiconductor memory device, several devices and methods have been currently developed, such as, a parallel bit test method.
The parallel bit test method may employ an exclusive OR (XOR) logic circuit or an exclusive NOR (XNOR) logic circuit. In other words, the same data may be written to a plurality of memory cells, and then read and subjected to logic operation by the XOR or XNOR logic circuits. When the read data is at the same logic state, a corresponding cell may be determined as accepted; and when any of the read data is at a different logic state, the corresponding cell may be determined as failed. Accordingly, the parallel bit test method may reduce testing time.
Further, in the parallel bit test, the test operation may be performed by a tester. The tester may generate control signals including a command, an address, and a test data pattern according to a user-programmed order, and may apply the control signals to the chips to be tested. For example, to test the semiconductor memory device, test data may be written to the address, and the data may be read from the address and output as DQ data. The tester may then compare the DQ data output from the semiconductor memory device with expected data (expected as an output) to determine the condition (e.g., pass or fail) of the semiconductor memory device. Accordingly, a user can recognize a failed semiconductor memory device (or the address) and may perform a suitable repair process using the address.
However, a tester used for the parallel bit test method may have only a limited number of DQ pins, making it difficult to test a plurality of semiconductor memory devices or chips. For example, a tester with 16 DQ pins may be capable of simultaneously testing two semiconductor memory devices by performing alternating testing by 8 bits, however, the tester with 16 DQ pins may not be able to simultaneously test three or more semiconductor memory devices. Accordingly, there may be a need for a scheme capable of simultaneously testing a plurality of semiconductor memory devices using an existing tester.